1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Description of the Related Art
In recent years, a matrix converter has been known as a direct-link-type conversion circuit which does not require a direct current (DC) smoothing circuit including, for example, an electrolytic capacitor or a DC reactor, in a power conversion circuit that performs alternating current (AC)/AC conversion, AC/DC conversion, and DC/AC conversion using a semiconductor element. Since the matrix converter is used at an AC voltage, a plurality of switching devices forming the matrix converter require a bidirectional switching device which can control a current in the forward direction and in the reverse direction.
In recent years, the bidirectional switching device having the following structure has been proposed in terms of reducing the size and weight of a circuit, improving efficiency and response, and reducing costs: two reverse blocking insulated gate bipolar transistors (IGBTs) are connected in inverse parallel to each other, as illustrated in the equivalent circuit diagram of FIG. 9. FIG. 9 is a circuit diagram illustrating the equivalent circuit of the bidirectional switching device using the reverse blocking IGBT. The inverse parallel connection structure of the reverse blocking IGBTs has the advantage that a diode for blocking a reverse voltage is not required. That is, the reverse blocking IGBT means a device which equalizes the reverse breakdown voltage to the forward breakdown voltage and has high reliability of breakdown voltage. In the general IGBT which is used in the power conversion circuit according to the related art, an effective reverse breakdown voltage is not required, similarly to the general transistor or insulated gate field effect transistor (MOSFET) without a reverse breakdown voltage. Therefore, an IGBT which has a reverse breakdown voltage lower than a forward breakdown voltage and has low reliability of breakdown voltage is enough for the bidirectional switching device.
Next, the structure of the reverse blocking IGBT according to the related art will be described. FIG. 8 is a cross-sectional view schematically illustrating the cross-sectional structure of the reverse blocking IGBT according to the related art. FIG. 8 is described in JP 2006-80269 A (Patent Document 1). The reverse blocking IGBT according to the related art has a structure in which an active region 110 is provided at the center, a breakdown voltage structure region 120 is provided in an outer circumferential portion surrounding the active region 110, and a p-type isolation layer 31 is provided so as to surround the outer circumference of the breakdown voltage structure region 120. Therefore, the depth of the p-type isolation layer 31 needs to be very large in order to form the p-type isolation layer 31 using only thermal diffusion from one main surface of a semiconductor substrate and a high-temperature and a long-term thermal diffusion (drive-in) process is involved. In general, the thermal diffusion is performed in an oxidation atmosphere. The reason is as follows. When an oxide film is formed on the surface of the semiconductor substrate, ions are confined in the semiconductor substrate and the dissipation of ions from the surface of the substrate to the outside of the substrate is prevented by thermal diffusion. In some cases, when the oxide film with a thickness that is more than necessary does not need to be formed during thermal diffusion in terms of the design of the device, oxygen partial pressure is reduced and a heat treatment is performed in a mixed gas atmosphere including other gases (for example, argon (Ar) and nitrogen (N2)) or the heat treatment is performed in an inert gas atmosphere without including oxygen.
The active region 110 illustrated in FIG. 8 is a main current path of a vertical IGBT including, for example, an n− drift region 21, a p-type base region 22, an n+ emitter region 23, a gate insulating film 24, a gate electrode 25, an interlayer insulating film 26, an emitter electrode 29, a p-type collector region 27, and a collector electrode 28. The p-type isolation layer 31 is a p-type region which is formed by the thermal diffusion of boron (B) at a depth that extends from the front surface of the semiconductor substrate to the p-type collector region 27 provided on the rear surface side. A termination portion of a pn junction surface between the p-type collector region 27 and the n− drift region 21, which is a reverse breakdown voltage junction, is not exposed from a side end surface 30 of a chip which is a cutting surface during chipping, but is exposed from a surface 32 of the breakdown voltage structure region 120 that is protected by an insulating film by the p-type isolation layer 31. Therefore, the reverse blocking IGBT including the p-type isolation layer 31 can improve the reliability of the reverse breakdown voltage.
FIG. 5((a) to (d)) and FIG. 6((a) to (d)) are cross-sectional views sequentially illustrating the manufacturing steps of an impurity diffusion process for forming a p-type isolation layer 104 of the reverse blocking IGBT using coating diffusion and ion implantation, respectively. FIG. 5 is a cross-sectional view illustrating the state of the isolation layer which is being formed by coating diffusion according to the related art. FIG. 6 is a cross-sectional view illustrating the state of the isolation layer which is being formed by ion implantation according to the related art. FIG. 7 is a cross-sectional view illustrating the end structure of a reverse blocking IGBT according to the related art. FIG. 7(a) illustrates the reverse blocking IGBT in which an isolation layer is formed by the diffusion layer that is formed by the manufacturing steps illustrated in FIGS. 5 and 6 so as to pass through a semiconductor substrate. First, a thermally-oxidized film 101 with a thickness of about 1.5 μm to 2.5 μm is formed as a dopant mask on the front surface of a semiconductor substrate 100 with a large thickness of 500 μm or more which is made of silicon (Si) as a semiconductor material (FIG. 5(a) and FIG. 6(a)).
Then, the thermally-oxidized film 101 is patterned to form an opening portion 102 through which impurities for forming the isolation layer are introduced (FIG. 5(b) and FIG. 6(b)). Then, a boron source 103, which is impurities, is coated into the opening portion 102 to form a shallow boron deposit layer (or boron ion implantation 105 is performed for a portion of the semiconductor substrate 100 which is exposed through the opening portion 102 of the thermally-oxidized film 101) (FIG. 5(c) and FIG. 6(c)). Then, the thermally-oxidized film 101 which is used as a dopant mask for the selective diffusion of boron (diffusion for the p-type isolation layer) is removed. Then, a heat treatment is performed at a high temperature (1300° C.) for a long time (100 hours to 200 hours) to form the p-type diffusion layer 104 with a depth of about 100 μm to 200 μm (FIG. 5(d) and FIG. 6(d)). The p-type diffusion layer 104 is used as the isolation layer.
Then, a process (not illustrated) of forming an oxide film on the front surface of the semiconductor substrate 100 surrounded by the p-type diffusion layer 104 again to form a MOS gate structure and a necessary front-surface-side functional region is performed. Then, the rear surface of the semiconductor substrate 100 is ground and removed such that the bottom of the p-type diffusion layer 104 is exposed, as represented by a dashed line, thereby reducing the thickness of the semiconductor substrate 100 (FIG. 5(d) and FIG. 6(d)). A rear surface structure including a p-type collector region and a collector electrode (which are not illustrated) is formed on the ground rear surface and the semiconductor substrate 100 is cut along a scribe line 108 which is disposed in a central portion of the p-type diffusion layer 104. The reverse blocking IGBT which is cut into a chip is illustrated in the cross-sectional views of FIG. 7(a) and FIG. 8.
However, as illustrated in FIGS. 5 and 6, in the reverse blocking IGBT in which the p-type isolation layer is formed by coating diffusion or ion implantation, a high-temperature and long-term thermal diffusion process is needed in order to form a deep p-type isolation layer as described above. As a result, during the high-temperature and long-term thermal diffusion process, an oxygen atom is introduced between the lattices in the semiconductor substrate and an oxygen precipitate, the phenomenon in which oxygen is changed to a donor, or a crystal defect occurs. When the crystal defect is introduced, there is a concern that the amount of leakage current will increase at the pn junction in the semiconductor substrate or the breakdown voltage and reliability of the insulating film formed on the semiconductor substrate will be significantly reduced.
In order to solve the problems caused by the high-temperature and long-term thermal diffusion process, a plurality of methods have been developed which reduce the diffusion depth of the p-type isolation layer to shorten the time required for the high-temperature thermal diffusion process. For example, there is a method which forms a V-shaped groove in the rear surface of a semiconductor substrate to reduce the depth of the isolation layer, thereby shortening the time required for a high-temperature thermal diffusion process for forming an isolation layer (for example, see the following Patent Document 2 to Patent Document 4). FIG. 7(b) illustrates an example of the end structure of a reverse blocking IGBT manufactured by U.S. Pat. No. 7,741,192, JP 2006-303410 A, and JP 2011-181770 A (Patent Document 2 to Patent Document 4, respectively). In addition, a method has been known which forms a trench 109 having a vertical side wall with a depth of depth 200 μm from the front surface of a semiconductor substrate 100 and forms a isolation layer 104b with a small depth on the side wall, thereby reducing the time required for a high-temperature thermal diffusion process, as illustrated in the cross-sectional view of FIG. 10. FIG. 10 is a cross-sectional view illustrating the structure of a reverse blocking IGBT according to the related art including an isolation layer which is formed using a trench. In FIG. 10, reference numeral 106 indicates a p-type collector region, reference numeral 108 indicates a scribe line, and reference numeral 111 indicates a MOS gate structure provided on the front surface side of a substrate.
In the related art, as the semiconductor substrate which is used to manufacture a high breakdown voltage power device, a silicon semiconductor substrate (hereinafter, referred to as an FZ silicon semiconductor substrate) has been used which is cut from a silicon single crystal (hereinafter, referred to as an FZ silicon single crystal) produced by a floating zone (FZ) method using polysilicon (hereinafter, referred to as FZ polysilicon). The FZ silicon semiconductor substrate has advantages including that dislocation included in the crystal is small and the content of oxygen is small, as compared to a silicon semiconductor substrate (hereinafter, referred to as a CZ silicon semiconductor substrate) that is cut from a silicon single crystal (hereinafter, referred to as a CZ silicon single crystal) produced by a Czochralski (CZ) method. Therefore, the FZ silicon single crystal is particularly indispensable as a silicon crystal for a power device with a high breakdown voltage and high current capacity. An FZ silicon semiconductor substrate with a large diameter is required in order to reduce the costs of the device. However, it is difficult to increase the diameter of the FZ silicon semiconductor substrate, as compared to the CZ silicon semiconductor substrate.
In general, as described above, FZ polysilicon is used as a raw material for the FZ silicon single crystal. However, the FZ polysilicon which is required as a raw material in the FZ method needs to have high purity, to be less likely to be cracked or broken, to have a uniform grain-boundary structure, to have a diameter suitable for the FZ silicon single crystal to be produced, and to have a cylindrical shape which is flat, has a large crank, and has a good surface state. Manufacturing yield or productivity in the production of the FZ polysilicon is significantly less than that in the production of nugget-shaped polysilicon used in the CZ method (hereinafter, referred to as CZ polysilicon). There is an increasing demand for the CZ polysilicon with a diameter of 300 mm. A method has been known which produces an FZ silicon single crystal with a large diameter, using, as a raw material, a silicon single crystal produced by the CZ method capable of producing a large-diameter single crystal silicon stably (compared to the FZ method), instead of the FZ polysilicon according to the related art (for example, see the following Patent Document 5). Hereinafter, a silicon semiconductor substrate which is cut from the FZ silicon single crystal produced by this method is referred to as a CZ-FZ silicon semiconductor substrate.
However, as described above, in the method disclosed in the above-mentioned Patent Document 2 to Patent Document 4 in which the V-shaped groove is formed in the rear surface of the semiconductor substrate, the depth of the p-type diffusion layer 104a from the front surface of the substrate is reduced to reliably shorten the thermal diffusion time at a high temperature. However, when the depth of the p-type diffusion layer 104a is too small, another problem occurs. Specifically, when the depth of the diffusion layer 104a from the front surface of the substrate is reduced in order to shorten the thermal diffusion time at a high temperature, the depth of the V-shaped groove needs to be increased by a value corresponding to the reduction in the depth. As a result, a new problem occurs, i.e., the semiconductor substrate 100 is likely to be broken.
In the method which forms the p-type isolation layer 104b using the trench 109 with the side wall vertical to the main surface to reduce the thermal diffusion time at a high temperature as illustrated in FIG. 10, the following problem occurs. For example, when a typical dry etching device is used, the time required to etch each trench 109 with a depth of about 200 μm is about 100 minutes. Therefore, for example, when the p-type isolation layer 104b is formed using the trench 109, the lead time increases and the number of maintenances increases.
In the high-temperature and long-term thermal diffusion process described with reference to FIGS. 5 to 7, when the above-mentioned CZ-FZ silicon semiconductor substrate is used, the yield of the semiconductor device is reduced (lowered) by the influence of crystal defects which synergistically occur due to vacancies that are included in the substrate at the beginning (before a semiconductor device manufacturing process) and crystal defects which newly occur in the semiconductor substrate due to an atmosphere gas species during a thermal diffusion process, as compared to the case in which the FZ silicon semiconductor substrate according to the related art is used.
That is, a precipitate is generated in the semiconductor substrate depending on the heat treatment condition. A crystal defect, such as a stacking fault, occurs due to the precipitate. There is a concern that the crystal defect will have an adverse effect on the electrical characteristics of the semiconductor device which is manufactured using the semiconductor substrate. A representative example of the crystal defect is an oxygen precipitate (SiO2) which is generated when a heat treatment is performed on the CZ silicon semiconductor substrate. Oxygen which is dissipated from a quartz crucible, which is a container, while a CZ silicon ingot (CZ silicon crystal) is being pulled up is introduced into the CZ silicon ingot and is precipitated as SiO2 when a heat treatment is performed.
When the crystal defect which occurs with the precipitation of SiO2 is present in the vicinity of the pn junction of the semiconductor device, junction leakage or breakdown voltage failure is caused by the crystal defect. Therefore, in a horizontal semiconductor device, such as large scale integration (LSI), in general, measures to perform a heat treatment to perform the oxygen precipitate from being generated in an active portion in the vicinity of the front surface of the semiconductor substrate are taken. In a high-power vertical semiconductor device, such as an IGBT, a current flows in the entire semiconductor substrate from the front surface to the rear surface of the semiconductor substrate. Therefore, only the structure in which the heat treatment is performed on the CZ silicon semiconductor substrate to prevent the generation of the oxygen precipitate in the vicinity of the front surface of the substrate is not sufficient.
Therefore, in general, the FZ silicon ingot is produced by the FZ method which can prevent the mixture of oxygen during the production of the ingot, in order to manufacture the semiconductor substrate used in the vertical semiconductor device. The use of the FZ silicon ingot makes it possible to prevent the generation of the oxygen precipitate and to reduce the deterioration of the electrical characteristics of the vertical semiconductor device in which a current flows in the entire surface of the substrate. However, precipitates other than the oxygen precipitate are generated when the heat treatment is performed on the semiconductor substrate.
In recent years, with an increase demand for a polysilicon rod material which is a raw material of the FZ silicon ingot, the FZ silicon ingot has been produced using the CZ silicon ingot, not the polysilicon rod, as a raw material. In this method, when oxygen included in the CZ silicon ingot is diffused to the outside during melting using induction heating and recrystallization is performed, the concentration of oxygen included in the FZ silicon ingot is reduced and a FZ silicon ingot with a low oxygen concentration is produced.
However, in the CZ-FZ silicon semiconductor substrate which is cut from the FZ silicon ingot that is produced using the CZ silicon ingot, when a heat treatment is performed at a high temperature (for example, 1300° C.) for a long time (for example, 100 hours) in order to form a deep conductive layer, in some cases, a precipitate is generated and the electrical characteristics of the semiconductor device deteriorate. Microscopic analysis proves that the precipitate is a nitrogen precipitate (α-Si3N4). The nitrogen precipitate is caused by a heat treatment which is performed in an atmosphere including nitrogen. As a method for preventing the generation of the nitrogen precipitate, there is a method which performs a heat treatment in a mixed gas atmosphere of argon and oxygen. In a high-temperature and long-term heat treatment which is performed in a mixed gas atmosphere of argon and oxygen, argon is generally used as a raw material gas, which results in an increase in costs.
The invention has been made in order to solve the above-mentioned problems of the related art and an object of the invention is to provide a method for manufacturing a semiconductor device which can suppress the occurrence of crystal defects in a silicon semiconductor substrate due to high-temperature and long-term thermal diffusion, even when including a step of performing the high-temperature and long-term thermal diffusion at a temperature of 1290° C. or more for a time of 100 hours or more to form a deep diffusion layer using a silicon semiconductor substrate that is cut from an FZ silicon crystal produced with a CZ silicon crystal.